#pragma once
enum SIEU_OP{
    SADD_src1_r_SIEU, //op = 111_0000_100， execution cycle = 1
    SADD_src1_imm, //op = 111_1000_100, execution cycle = 1
    SADDU_src1_r_SIEU, //op = 110_0000_100, execution cycle = 1
    SADDU_src1_imm_SIEU, //op = 110_1000_100, execution cycle = 1
    SADDA_src1_r_SIEU, //op = 111_0111_000, execution cycle = 1
    SADDA_src1_imm, //op = 111_1111_000, execution cycle = 1
    SADD32_src1_r_SIEU, //op = 101_0000_100,execution cycle = 1
    SADD32_src1_imm, //op = 101_1000_100, execution cycle = 1
    SADDU32_src1_r_SIEU, //op = 100_0000_100, execution cycle = 1
    SADDU32_src1_imm_SIEU, //op = 100_1000_100, execution cycle = 1
    SSUB_src1_r_SIEU, //op = 111_0000_000, execution cycle = 1
    SSUB_src1_imm, //op = 111_1000_000, execution cycle = 1
    SSUBU_src1_r_SIEU, //op = 110_0000_000, execution cycle = 1
    SSUBU_src1_imm, //op = 110_1000_000, execution cycle = 1
    SSUBC, //op = 110_0000_010, execution cycle = 1
    SSUBA_src1_r_SIEU, //op = 111_0111_001, execution cycle = 1
    SSUBA_src1_imm, //op = 111_1111_001, execution cycle = 1
    SSUB32_src1_r_SIEU, //op = 101_0000_000, execution cycle = 1
    SSUB32_src1_imm, //op = 101_1000_000, execution cycle = 1
    SSUBU32_src1_r_SIEU, //op = 100_0000_000, execution cycle = 1
    SSUBU32_src1_imm, //op = 100_1000_000, execution cycle = 1
    SSUBC32, //op = 100_0000_010, execution cycle = 1
    SSAT, //op = 111_0101_000, execution cycle = 1
    SSAT32, //op = 101_0101_000, execution cycle = 1
    SNEG, //op = 111_0100_100, execution cycle = 1
    SNEG32, //op = 101_0100_100, execution cycle = 1
    SABS, //op = 111_0100_000, execution cycle = 1
    SABS32, //op = 101_0100_000, execution cycle = 1
    SMAX, //op = 111_0001_100, execution cycle = 1
    SMAXU, //op = 110_0001_100, execution cycle = 1
    SMAX32, //op = 101_0001_100, execution cycle = 1
    SMAXU32, //op = 100_0001_100, execution cycle = 1
    SMIN, //op = 111_0001_000, execution cycle = 1
    SMINU, //op = 110_0001_000, execution cycle = 1
    SMIN32, //op = 101_0001_000, execution cycle = 1
    SMINU32, //op = 100_0001_000, execution cycle = 1
    SEQ_src1_r, //op = 111_0010_000, execution cycle = 1
    SEQ_src1_imm, //op = 111_1010_000, execution cycle = 1
    SLT_src1_r, //op = 111_0010_010, execution cycle = 1
    SLT_src1_imm, //op = 111_1010_010, execution cycle = 1
    SLTU_src1_r, //op = 110_0010_010, execution cycle = 1
    SLTU_src1_imm, //op = 110_1010_010, execution cycle = 1
    SEQ32_src1_r, //op = 101_0010_000, execution cycle = 1
    SEQ32_src1_imm, //op = 101_1010_000, execution cycle = 1
    SLT32_src1_r, //op = 101_0010_010, execution cycle = 1
    SLT32_src1_imm, //op = 101_1010_010, execution cycle = 1
    SLTU32_src1_r,  //op = 100_0010_010, execution cycle = 1
    SLTU32_src1_imm, //op = 100_1010_010, execution cycle = 1
    SMOV_SIEU, //op = 111_1110_001, execution cycle = 1
    SMVCGC, //op = 111_1110_010, execution cycle = 1/2
    SMVCCG, //op = 111_1110_011, execution cycle = 1/2/3
    SMOVI_SIEU, //op 80位指令, execution cycle = 1
    SMOVI24_SIEU, //op 40位指令, execution cycle = 1
    SAND_src1_r, //op = 111_0011_000, execution cycle = 1
    SAND_src1_imm, //op = 111_1011_000, execution cycle = 1
    SOR_src1_r, //op = 111_0011_010, execution cycle = 1
    SOR_src1_imm, //op = 111_1011_010, execution cycle = 1
    SXOR_src1_r, //op = 111_0011_100, execution cycle = 1
    SXOR_src1_imm, //op = 111_1011_100, execution cycle = 1
    SNOT_src1_r, //op = 111_0011_110, execution cycle = 1
    SNOT_src1_imm, //op = 111_1011_110, execution cycle = 1
    SLZD, //op = 111_0101_100, execution cycle = 1
    SLZD32, //op = 101_0101_100, execution cycle = 1
    SSHFLL32_src1_r, //op = 0000_0000_00, execution cycle = 1
    SSHFLL32_src1_imm, //op = 0010_0000_00, execution cycle = 1
    SSHFLL_src1_r, //op = 0100_0000_00, execution cycle = 1
    SSHFLL_src1_imm, //op = 0110_0000_00, execution cycle = 1
    SSHFLR32_src1_r, //op = 0000_1000_00, execution cycle = 1
    SSHFLR32_src1_imm, //op = 0010_1000_00, execution cycle = 1
    SSHFLR_src1_r, //op = 0100_1000_00, execution cycle = 1
    SSHFLR_src1_imm, //op = 0110_1000_00, execution cycle = 1
    SSHFAR32_src1_r, //op = 0001_0000_00, execution cycle = 1
    SSHFAR32_src1_imm, //op = 0011_0000_00, execution cycle = 1
    SSHFAR_src1_r, //op = 0101_0000_00, execution cycle = 1
    SSHFAR_src1_imm, //op = 0111_0000_00, execution cycle = 1
    SBCLR32, //op = 0000_0010_00, execution cycle = 1
    SBCLR, //op = 0100_0010_00, execution cycle = 1
    SBSET32, //op = 0000_1010_00, execution cycle = 1
    SBSET, //op = 0100_1010_00, execution cycle = 1
    SBEX32, //op = 0001_0010_00, execution cycle = 1
    SBEX, //op = 0101_0010_00, execution cycle = 1
    SBTST32, //op = 0001_1010_00, execution cycle = 1
    SBTST, //op = 0101_1010_00, execution cycle = 1
    SBEXT32, //op = 0010_0010_00, execution cycle = 1
    SBEXT, //op = 0110_0010_00, execution cycle = 1
    SBEXT32U, //op = 0010_1010_00, execution cycle = 1
    SBEXTU, //op = 0110_1010_00, execution cycle = 1
    SBALE2, //op = 0000_0100_00, execution cycle = 1
    SBALE2H, //op = 0000_1100_00, execution cycle = 1
    SBALE2LH, //op = 0001_0100_00, execution cycle = 1
    SBALE2HL, //op = 0001_1100_00, execution cycle = 1
    SBALE4H, //op = 0010_0100_00, execution cycle = 1
    SBALE4L, //op = 0010_1100_00, execution cycle = 1
    SSBALE2, //op = 0011_0100_00, execution cycle = 1
    SSBALE4, //op = 0011_1100_00, execution cycle = 1
    SUBALE4H, //op = 0100_0100_00, execution cycle = 1
    SUBALE4L, //op = 0100_1100_00, execution cycle = 1
    SITL2, //op = 0101_0100_00, execution cycle = 1
    SITL4, //op = 0101_1100_00, execution cycle = 1
    //TODOszy:补全SIEU的全部操作
};